1. Field of the Invention
The present invention relates to chip size reduction of a semiconductor memory device.
2. Description of the Related Art
A DRAM and an SRAM are typically used as the semiconductor memory device. As is well known in the art, the DRAM is less expensive and has a larger capacity than the SRAM, but requires the refreshing operation. On the other hand, the SRAM is convenient without any requirement of the refreshing operation, but is more expensive and has a smaller capacity than the DRAM.
A virtual SRAM (referred to as VSRAM or PSRAM) is known as a semiconductor memory device having the advantages of both the DRAM and the SRAM. The virtual SRAM has a memory cell array of dynamic memory cells like the DRAM and includes a refresh controller for execution of the refreshing operation. An external device (for example, a CPU) connecting with the virtual SRAM can thus gain access to the virtual SRAM (for reading and writing data) without specifically being aware of the refreshing operation.
The size of the semiconductor chip is expanded with an increase in storage capacity of the virtual SRAM. The large chip size tends to extend the length of the internal connection line, which may cause deterioration of the operating performance, such as the lowered operating speed, due to a signal delay. It is accordingly desired to attain chip size reduction even in the case of the increased storage capacity.
The requirement of chip size reduction is not restricted to the virtual SRAM but is common to a diversity of semiconductor memory devices like the DRAM and the SRAM.
The object of the present invention is thus to solve the problems discussed above and to provide a technique of attaining chip size reduction of a semiconductor memory device, such as a virtual SRAM.
In order to attain at least part of the above and the other related objects, the present invention is directed to a first semiconductor memory device including: a first memory cell block and a second memory cell block, in each of which memory cells are arranged in a matrix; and a common preamplifier/write driver shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells. The common preamplifier/write driver is located between the first memory cell block and the second memory cell block.
This semiconductor memory device has one common preamplifier/write driver shared by the first memory cell block and the second memory cell block. The common preamplifier/write driver, the first memory cell block, and the second memory cell block are arranged in the direction parallel to the columns of the memory cells. In the case of no sharing of the preamplifier/write driver, two preamplifier/write drivers are provided in the direction parallel to the columns of the memory cells. The arrangement of the first semiconductor device of the present invention thus effectively attains size reduction of the semiconductor chip in the direction parallel to the columns of the memory cells.
When the common preamplifier/write driver is not disposed between the first memory cell block and the second memory cell block but is located on an outer end of either of the two memory cell blocks in the direction parallel to the columns of the memory cells, there is a relatively large difference between the length of a connection line of the common preamplifier/write driver with one memory cell block and the length of a connection line of the common preamplifier/write driver with the other memory cell block. In the semiconductor device of the present invention, however, the common preamplifier/write driver is located between the two memory cell blocks. Compared with the structure where the common preamplifier/write driver is located on the outer end of either of the two memory cell blocks, there is a significantly smaller difference between the length of the connection line of the common preamplifier/write driver with one memory cell block and the length of the connection line of the common preamplifier/write driver with the other memory cell block. This arrangement desirably prevents deterioration of the operating performance, due to a signal delay according to the varied length of the connection line.
In accordance with one preferable application, the first semiconductor memory device further has multiple bit line pairs connecting the first memory cell block with the second memory cell block. The common preamplifier/write driver includes: a preamplifier circuit and a write driver circuit that are provided on each of the bit line pairs and are connected in parallel to the bit line pair; a first switch that is disposed between the first memory cell block and contacts of the preamplifier circuit and the write driver circuit with the bit line pair, in order to connect the preamplifier circuit and the write driver circuit with the first memory cell block; and a second switch that is disposed between the second memory cell block and the contacts, in order to connect the preamplifier circuit and the write driver circuit with the second memory cell block. The first switch and the second switch are controlled respectively in response to a first block selection signal and a second block selection signal, which respectively correspond to the first memory cell block and the second memory cell block.
This readily actualizes the common preamplifier/write driver.
In accordance with another preferable application, the first semiconductor memory device further has a common column address decoder shared by the first memory cell block and the second memory cell block. The common column address decoder is located adjacent to the common preamplifier/write driver between the first memory cell block and the second memory cell block.
In this application, the common column address decoder shared by the first memory cell block and the second memory cell block is located adjacent to the common preamplifier/write driver between the first memory cell block and the second memory cell block. This arrangement attains further reduction of the chip size in the direction parallel to the columns of the memory cells.
Compared with the structure where the common column address decoder is not disposed between the first memory cell block and the second memory cell block but is located on the outer end of either of the two memory cell blocks in the direction parallel to the columns of the memory cells, there is a significantly smaller difference between the length of the connection line of the common column address decoder with the first memory cell block and the length of the connection line of the common column address decoder with the second memory cell block. This arrangement desirably prevents deterioration of the operating performance, due to a signal delay according to the varied length of the connection line.
The present invention is also directed to a second semiconductor memory device including: a first memory cell block and a second memory cell block, in each of which memory cells are arranged in a matrix; and a common column address decoder shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cell. The common column address decoder is located between the first memory cell block and the second memory cell block.
In this semiconductor memory device, the common column address decoder shared by the first and the second memory cell blocks is located between the first memory cell block and the second memory cell block, which are aligned in the direction parallel to the columns of the memory cells. Like the first semiconductor memory device, this arrangement desirably attains reduction of the chip size in the direction parallel to the columns of the memory cells.
Compared with the structure where the common column address decoder is not disposed between the first memory cell block and the second memory cell block but is located on the outer end of either of the two memory cell blocks in the direction parallel to the columns of the memory cells, there is a significantly smaller difference between the length of the connection line of the common column address decoder with the first memory cell block and the length of the connection line of the common column address decoder with the second memory cell block. This arrangement desirably prevents deterioration of the operating performance, due to a signal delay according to the varied length of the connection line.
In one preferable embodiment of both the first semiconductor memory device and the second semiconductor memory device, the first memory cell block and the second memory cell block respectively have a first column driver and a second column driver disposed on either side of the common column address decoder. The common column address decoder has: a column address decoding module that supplies a set of column selection signals, which are converted corresponding to an input column address, commonly to the first column driver and the second column driver; and a column drive enable signal generation module that supplies a first column drive enable signal and a second column drive enable signal respectively to the first column driver and the second column driver, in order to enable operations of the first column driver and the second column driver.
This arrangement readily actualizes the common column decoder.